Image sensor and light source driver integrated in a same semiconductor package

ABSTRACT

An apparatus is described that includes an image sensor and a light source driver circuit integrated in a same semiconductor chip package. The image sensor includes visible light pixels and depth pixels. The depth pixels are to sense light generated with a light source drive signal. The light source drive signal is generated with the light source driver circuit.

RELATED CASES

This application is a continuation of and claims the benefit of U.S.patent application Ser. No. 14/579,825, titled “IMAGE SENSOR AND LIGHTSOURCE DRIVER INTEGRATED IN A SAME SEMICONDUCTOR PACKAGE”, filed Dec.22, 2014, which is incorporated by reference in its entirety.

CROSS-REFERENCE TO RELATED APPLICATIONS

NOTICE: More than one reissue application has been filed for the reissueof U.S. Pat. No. 10,257,455. The reissue applications are U.S. patentapplication Ser. No. 17/225,813 (the present application) filed on Apr.8, 2021 and U.S. Ser. No. 17/323,319 (a continuation reissue applicationclaiming benefit of the present application) filed herewith.

This application is an application for reissue of U.S. Pat. No.10,257,455, issued from U.S. patent application Ser. No. 15/426,561,filed on Feb. 7, 2017, which in turn is a continuation of U.S. patentapplication Ser. No. 14/579,825, filed on Dec. 22, 2014 (now U.S. Pat.No. 9,581,696).

FIELD OF THE INVENTION

The field of invention pertains generally to camera technology and, morespecifically, to an image sensor and light source driver integrated in asame semiconductor package.

BACKGROUND

Many existing computing systems include one or more traditional imagecapturing cameras as an integrated peripheral device. A current trend isto enhance computing system imaging capability by integrating depthcapturing into its imaging components. Depth capturing may be used, forexample, to perform various intelligent object recognition functionssuch as facial recognition (e.g., for secure system un-lock) or handgesture recognition (e.g., for touchless user interface functions).

One depth information capturing approach, referred to as“time-of-flight” imaging, emits light from a system onto an object andmeasures, for each of multiple pixels of an image sensor, the timebetween the emission of the light and the reception of its reflectedimage upon the sensor. The image produced by the time of flight pixelscorresponds to a three-dimensional profile of the object ascharacterized by a unique depth measurement (z) at each of the different(x,y) pixel locations.

As many computing systems with imaging capability are mobile in nature(e.g., laptop computers, tablet computers, smartphones, etc.), theintegration of a light source (“illuminator”) into the system to achievetime-of-flight operation presents a number of design challenges such ascost challenges, packaging challenges and/or power consumptionchallenges.

SUMMARY

An apparatus is described that includes an image sensor and a lightsource driver circuit integrated in a same semiconductor chip package.The image sensor includes visible light pixels and depth pixels. Thedepth pixels are to sense light generated with a light source drivesignal. The light source drive signal is generated with the light sourcedriver circuit.

An apparatus is described that includes, within a same semiconductorchip package, means for generating a drive signal for a light source,means for responding to light generated from the drive signal andreflected from an object to generate analog depth profile informationfor the object and means for digitizing the analog depth profileinformation.

FIGURES

The following description and accompanying drawings are used toillustrate embodiments of the invention. In the drawings:

FIG. 1a shows a depiction of an embodiment of an integrated image sensorand light source driver;

FIG. 1b shows another depiction of an embodiment of an integrated imagesensor and light source driver;

FIG. 2 shows a system diagram of an integrated image sensor and lightsource driver;

FIG. 3a shows a system diagram of a light source driver;

FIG. 3b shows a diagram of a core light source driver;

FIG. 3c shows a diagram of a optical output power circuit;

FIG. 4 shows a diagram of a timing and control circuit;

FIG. 5a shows a first methodology performed by an integrated imagesensor and light source driver;

FIG. 5b shows a second methodology performed by an integrated imagesensor and light source driver;

FIG. 6a shows another embodiment of an integrated image sensor and lightsource driver;

FIG. 6b shows yet another embodiment of an integrated image sensor andlight source driver;

FIG. 7 shows an embodiment of a 2D/3D camera system having an integratedimage sensor and light source driver;

FIG. 8 shows an embodiment of a computing system having 2D/3D camerasystem having an integrated image sensor and light source driver.

DETAILED DESCRIPTION

FIGS. 1a and 1b show different perspectives of an integrated imagesensor and light source driver 100 that addresses some of the challengesreferred to in the Background. As observed in FIGS. 1a and 1b, theintegrated image sensor and light source driver 100 includes an RGBZpixel array chip 101 that is stacked on an underlying integrated circuit102 having analog-to-digital (ADC) circuitry 103, timing and controlcircuitry 104 and light source driver circuitry 105. The underlyingintegrated circuit 102 is mounted on a package substrate 106 such thatthe entirely of the pixel array 101 and the underlying integratedcircuit 102 are contained within a same package 107.

The RGBZ pixel array chip 101 includes different kinds of pixels, someof which are sensitive to visible light (red (R), green (G) and blue(B)) and others of which are sensitive to IR light. The RGB pixels areused to support traditional “2D” visible image capture (traditionalpicture/video taking) functions. The IR sensitive pixels are used tosupport 3D depth profile imaging using time-of-flight techniques.

A camera system having both traditional image capture and time-of-flightdepth capture functions typically includes: 1) an illuminator (e.g., atleast one laser, laser array, LED or LED array to generate the IR lightfor the time-of-flight system); 2) an RGBZ pixel array; 3) drivercircuitry for the illuminator; and, 4) analog to digital conversioncircuitry and timing and control circuitry that, together with the RGBZpixel array, form a complete image sensor. Here, items 1) and 2) abovecan be viewed as the electro-optical components of the camera system anditems 3) and 4) can be viewed as the supporting electronics for theelectro-optical components. Notably, the integrated image sensor andlight source driver 100 of FIGS. 1a and 1b integrate most if not all ofitems 2), 3) and 4) above in a single package 107 which, in turn, shouldprovide for a cheaper and/or smaller form factor solution for theseitems as compared to prior art approaches.

For ease of drawing the ADC circuitry 103, timing and control circuitry104 and light source driver circuitry 105 are drawn not necessarily toscale and not showing any “underlap” beneath the pixel array 101. It isconceivable that some solutions may opt to place some portion or theentirety of any of the ADC circuitry 103, the timing and controlcircuitry 104 and the light source driver 105 beneath the pixel array101.

FIG. 1b shows an embodiment of a cross section of the pixel array 101stacked on the underlying semiconductor die 102. As observed in FIG. 1b,electrically conductive balls/bumps formed on the top surface of theunderlying integrated circuit 102 are aligned to make contact withconductive balls/bumps formed on the lower surface of the pixel array101.

The balls/bumps on the lower surface of the pixel array 101 areconnected to respective conductive vias within the pixel array substratethat electrically couple to respective traces formed within themetallization planes of the pixel array 101. As is known in the art, themetallization planes of the pixel array 101 provide biasing and/orsignaling to any transistors embedded in the upper surface of the pixelarray substrate as well as provide the output analog sense signalsgenerated by the pixel array's pixels. The metallization planes may bepart of a larger multilayer structure above the pixel array substratethat also includes filters (e.g., RGB filters for RGB pixels and IRfilters for Z pixels) and micro-lenses.

The underlying IC 102 also includes through-substrate conductive viasthat electrically connect its metallization layers to its underlyingcontact balls/bumps. Note that, as appropriate for any particularpackaging technology, any ball/bump of a pair of contacting balls/bumpsshown in FIG. 1b may be replaced with a pad/land instead of a ball/bump.Balls/bumps/pads may be disposed as an array, around the periphery orother arrangement on its corresponding die's surface. In an alternativeapproach, instead of a ball/bumps being formed on the lower side of theIC, the IC may include wire bond pads around its periphery and the ICmay be electrically coupled to the package substrate by wire bondingfrom these pads to the surface of the underlying substrate.

The package substrate 107 may be made from any typical planar boardtechnology (e.g., having alternatively layers of conductive andinsulating planes, where the insulating planes are composed of any of,e.g., FR4, ceramic, etc.). As observed in FIG. 1b, the package substrate107 also has conductive balls/bumps for electrical contact to the camerasystem into which the sensor and driver is integrated.

FIG. 2 shows a depiction of the system architecture 200 for integratedimage sensor and light source driver 100 of FIGS. 1a and 1b. As observedin FIG. 2 , the light source driver circuitry 205 provides a drivesignal 211 to the illuminator (not shown). The amplitude of the drivesignal determines the optical power of the light emitted from theilluminator. In an embodiment, the illuminator includes a photo-detectorthat generates a higher amplitude signal as the optical intensityemitted by the illuminator increases. According to the systemarchitecture 200 of FIG. 2 , the photo-detector signal 212 is receivedby the light source driver circuitry and incorporated into a controlledfeedback loop to control the amplitude of the drive signal 211.

The drive signal 211 may also be modulated, e.g., in the form of asinusoidal or clock signal, to implement continuous wave illumination.Timing and control circuitry 204 provides the modulation signal to thelight source driver circuitry 205. In the case where the modulationsignal is akin to a clock signal, one logic value of the clock signalcorresponds to the illuminator being “on” while the other logic valuecorresponds to the illuminator being “off”. As such, the illuminatorflashes light in an on-off-on-off fashion into the camera's field ofview. In various embodiments, the light source(s) of the illuminator maybe arranged as an array of vertical cavity side emitting laser diodes(VCSELs) or light emitting diodes (LEDs) each coupled to a same anodeterminal and a same cathode terminal (so that all VCSEL/LEDs of thearray turn on and off together), and where, the drive signal 211 fromthe light source driver 205 is coupled to one of the anode or cathode ofthe array.

The “Z” pixels of the RGBZ pixel array 201 effectively perform “3D”time-of-flight depth measurements by generating charge as a function ofthe time between when the illuminator's light was flashed “on” and whenthe flash's reflected light is received at the sensor. The Z pixelsreceive clock signals from timing and control circuitry 204 that eachhave a known phase relationship with the illuminator's clock signal. Inone embodiment, there are four such clock signals (e.g., 0°, 90°, 180°and 270° quadrature arms) provided to each region of the pixel array 201where a depth value is to be measured.

Here, Z pixels that are clocked by clocks of differing phase willcollect different amounts of charge for a same light flash. Collectedcharge signals from differently clocked Z pixels in a same/proximateregion of the sensor can be combined to generate a specifictime-of-flight value for the sensor region. In a typical implementation,such combination is made by the host system (e.g., processor orapplications processor) with an image signal processor. As such, the ADCcircuitry 203 typically converts analog signals representing the chargecollected by the individual Z pixels into digital values that areforwarded to the host system which subsequently calculates the depthinformation from the digitized pixel values. In other embodiments,various forms of image signal processing, including but not limited tothe calculation of the depth information from the pixels may beperformed by logic circuitry external to the host side (e.g., logiccircuitry disposed on a same semiconductor chip that includes the imagesensor or some other semiconductor chip included in the cameraperipheral).

The RGB pixels of the RGBZ pixel array 201 are used for “2D” traditionalimage capture and are respectively sensitive to red, green and bluevisible light within the camera's field of view. The ADC circuitry 203likewise receives analog signals from the RGB pixels of the pixel array201 and converts them to digital values that are forwarded to the hostsystem. Although a common approach includes RGB pixels for the visibleimage capture, other embodiments may use different colored pixel schemes(e.g., Cyan, Magenta and Yellow).

The timing and control circuit 204 generates respective clock signalsthat are sent to the light source driver 205, the pixel array 201 andthe ADC circuitry 203. Other signals, such as control signals generatedin response to commands or configuration information that is receivedfrom the host system and stored in configuration registers 208 may alsobe generated from the timing and control circuitry. For ease of drawingpurposes, FIGS. 1a and 1b do not depict the configuration registers 208of FIG. 2 .

Notably, because traditional image sensors do not have an integratedilluminator driver, traditional image sensor timing and control circuitsonly generate control and clocking signals for image sensor components(notably, the ADC circuitry 203 and the pixel array 201). By contrast,the timing and control circuit 204 in various embodiments may beconsidered unique because, apart from providing clock and controlsignals used for image reception, it also generates timing and controlcircuitry for a light source drive circuit 205. Note that,architecturally speaking, image sensor timing and control circuitry thatalso generates timing and/or control signals for a light source drivecircuit is believed to be unique whether or not the light source drivecircuit is integrated on the same semiconductor chip with the imagesensor timing and control circuitry.

FIGS. 3a through 3c show aspects of the laser driver circuit 205 of FIG.2 . As observed in FIG. 3a, the laser driver circuit 305 can be viewedas including a core driver circuit 301 and a power control circuit 302.The core driver circuit 301 provides the drive current that is driventhrough the light source. The core driver circuit 301 also receives awaveform (e.g., clock signal, sinusoid, etc.) as a modulation signal 303for the drive signal. As discussed above, the modulation signaldetermines the timing of the manner in which the light source isflashed.

The optical output power control circuit 302 provides to the core drivercircuit 301 a signal 304 that specifies the magnitude of the drivesignal. The magnitude of the drive signal, in turn, determines theoptical power emitted by the light source. In an embodiment, the powercontrol circuit 302 also receives the photodiode current (or anindication of the RMS or average value thereof) from the light sourcearray. As discussed in more detail below, the photodiode currentprovides an indication of the optical output power presently beingemitted by the light source, and, the optical output power controlcircuit 302 uses the photodetector current as an input into to acontrolled feedback loop. The optical output power control circuit 302may also receive an override optical power value that overrides theaforementioned feedback loop for, e.g., testing or manufacturingenvironments. Each of these features will be described more thoroughlyimmediately below.

FIG. 3b shows an embodiment of the core driver circuit 301. As observedin FIG. 3a, the core driver 301 includes a plurality of driver “slices”310 each having a drive transistor and an enable gate. In order toestablish a specific drive strength for the core driver 301, the coredriver 301 is configured to receive input information 311 that definesthe number of the slices to activate. According to the specificembodiment of FIG. 3 , the input information takes the form of a buswith each wire of the bus corresponding to an active/inactive signal fora particular slice.

Each of the driver slices also include a clock signal input 312 toreceive a digital clock signal. The clock signal modulates the currentbeing pulled by the drive transistors of the enabled slices such thatthe light source flashes in an on-off-on-off sequence as discussedabove. Because the set of driver slices present a large inputcapacitance at the clock signal input, an inverting drive buffer 313having sufficient output current drive strength to drive the clocksignal input capacitance is coupled to the clock signal input 312. Asobserved in FIG. 3b, the inverting drive buffer 313 and precedingbuffer/inverters 314 form a fan-up chain to increase the drive strengthof the drive buffer 313. A fan-up chain includes a series ofbuffers/inverters where each buffer/inverter in the chain providesgreater output drive strength that it's preceding buffer/inverter. Thus,per buffer/inverter output drive strength is essentially amplifiedmoving forward in the chain. In the embodiment of FIG. 3b, fourinverters produce sufficient drive strength at the output of invertingdrive buffer 313.

The core driver circuit 301 includes special, isolated upper and lowerpower rails VDD_DRVR 316 and VSS_DRVR 317. In an embodiment, each ofthese power rails 316, 317 is supplied by a respective external, off-dievoltage regulator (not shown) that is dedicated to the core drivercircuit. Multiple I/Os (balls/pads) of the core driver's semiconductorchip are reserved for each of the rails to ensure low resistance betweenthe regulators and the integrated sensor/driver package.

In an embodiment where the semiconductor die is wire bonded to thepackage substrate, multiple pads of the IC are reserved for both rails,and each of the multiple pads is double bonded to the package substrate(again, to reduce resistance between the package substrate and thesemiconductor chip). Here, as the core driver circuit may drivesignificant amounts of current, keeping resistance low along the supplyrails keep power dissipation low through the IC wire bonds.

The core driver circuit 301 also includes other circuitry to provide forelectro-static discharge (ESD) protection and isolation from the othercircuits on the semiconductor chip. With respect to ESD protection, itis pertinent to recognize that any node of the core driver circuit 301that is connected to a package I/O may receive a large amount of ESDcharge. These nodes include any of the VDD_DRVR 316, VSS_DRVR 317 andthe light source drive signal output node 318. In order to protect thecore driver circuit 301, the core driver circuit 301 should include acurrent pathway out of the circuit 301 from any of these nodes 316, 317,318 should they receive electro-static discharge.

FIG. 3b shows a first current path 320 out of the circuit 310 if theVDD_DRVR node 316 is charged, a second current path 321 out of thecircuit 310 if the drive signal output 318 is charged and third currentpath(s) 322 out of the circuit if the VSS_DRVR node 317 is charged.These paths 320, 321, 322 flow into “other” VSS nodes of thesemiconductor die (e.g., VSS nodes used by circuits of the semiconductordie other than the core driver 301).

Note that some of these paths 320, 322 flow through a bypass capacitor323 that resides between the VDD_DRVR and VSS_DRVR nodes. The bypasscapacitor 323 and an ESD clamp circuit 324 also help prevent thegeneration of a large, damaging voltage difference across the VDD_DRVR316 and VSS_DRVR 317 nodes as a consequence of being charged. Likewise,a large voltage is prevented from being generated at the light sourcedrive output by protective clamping diodes 325.

The core driver circuit 301, in driving the light source, may be askedto drive large amounts of current and therefore may have the propensityto act as a noise source for other circuits on the semiconductor die orotherwise within the package. As such, the core driver circuit 301 alsoincludes a number of isolation features.

A first isolation feature is the separate VDD_DRVR and VSS_DRVR supplyrails 316, 317 discussed above that are driven by their own voltageregulators (i.e., in an embodiment the voltage regulators do not driveother circuits besides the VDD_DRVR and VSS_DRVR rails respectiverails). A second isolation feature is the presence of isolation clamps326, 327 that reside at both points of contact between the core drivercircuit and the other VSS nodes. Here, the ESD protection paths out ofthe core driver circuit effectively couple the VSS_DRVR node to theother VSS nodes. Such coupling can permit noise generated by the coredriver circuit 301 to reach other circuits within the semiconductor die.The isolation clamps 326, 327 help squelch such noise coupling.

A fourth isolation feature is to implement the transistors of the coredriver in a “deep well” technology such as a deep N well technology. Adeep well technology embeds active devices in a well of a first dopantpolarity (e.g., P). Deeper within the substrate the first well isembedded within a larger well of opposite polarity (e.g., N) which isitself embedded within a substrate of first dopant polarity (e.g., P).The junctions of opposite polarity effectively create noise barriersbetween the active devices and the substrate. In some embodiments activedevices may also reside within the larger well.

A fifth isolation feature recognizes that the high currents generated bythe core drive circuit may generate hot carriers that induce photongeneration. The generation of photons, in turn, may interfere with theoperation of the sensor array. As such, in one embodiment, one of themetallization layers of the integrated circuit is used to form awide/large surface area of solid conductive material (e.g., metal) abovethe core driver circuit. The large conductive region above the coredriver acts as a shield that should substantially prevent any photonsgenerated by the core driver 301 from reaching other circuits such asthe pixel array.

FIG. 3c shows an embodiment of the power control circuit 302. Asobserved in FIG. 3c, the power control circuit 302 includes a finitestate machine 330. As is known in the art a finite state machine 330typically includes combinatorial logic 331 in front of a register 332where the register state feeds back to the combinatorial logic 331 andwhere the combinatorial logic 331 also receives another independentinput 333. In an embodiment, the combinatorial logic 331 is implementedwith a look-up table (e.g., implemented with, e.g., content addressableregister or memory cells). In other embodiments the combinatorial logic331 may be implemented with hardwired logic circuits or a combination ofa look-up table and hardwired logic implementations.

The register state corresponds to the output of the power controlcircuit 302 and defines which core driver slices are to be enabled. Theindependent input 333 provided to the combinatorial logic 331 of thefinite state machine corresponds to a photodetector current. Here, thelight source array is assumed to include a photodiode that provides anoutput signal that is proportional to the actual intensity of the lightthat the light source array is emitting (or, given that the opticalsignal is in the form of a periodic signal, the average or theroot-mean-square (RMS) of the photocurrent may be utilized). Thephotodetector signal is converted to digital form by an ADC circuit 334and provided to the combinatorial logic 331. The combinatorial logic 331determines a number of core driver slices to enable as a function of thecurrent number of core driver slices that are enabled and the currentphotodetector current.

In alternate implementations the finite state machine may be replacedwith a more traditional controlled feedback loop having a loop filterthat generates a signal whose value indicates the number of slices toenable by integrating an offset signal generated from, e.g., a desiredoptical power signal and an actual optical power signal derived from thephotodetector signal. The traditional feedback loop may be implementedwith digital and/or analog circuits.

Notably, the power control circuit also includes an over-ridemultiplexer 335 to effectively over-ride the determined number of slicesfrom the finite state machine and, instead, provide a more customizedindication of the number of slices to enable. The over-ride can be used,e.g., to set a stronger optical output signal than is typical tosimulate the illuminator being closer to an object of interest than itactually is, or, set a weaker optical output signal than is typical tosimulate the presence of the illuminator being farther away from anobject of interest than it actually is.

The customized number of slices may be provided directly fromconfiguration register space, or, may be provided from a look up table(LUT), hardwired logic or other circuitry 335 that determines thecorrect number of core driver slices to enable in response to a userprovided value for any of the following in configuration registerspace: 1) optical output power; 2) simulated additional distance away;3) simulated additional distance closer. The configuration registerspace may also include an “override enable” parameter that is used toset the channel select input of the override multiplexer 335 (such thatthe user provided value is used if the override is enabled).

FIG. 4 shows clocking circuitry for the laser driver circuit and pixelarray. The clocking circuitry of FIG. 4 may also provide clock signalsto the ADC circuitry. As observed in FIG. 4 the clocking circuitry canbe viewed as a component of the timing and control circuitry 104, 204 ofFIGS. 1a,b and 2.

As observed in FIG. 4 the clocking circuitry includes a phase lockedloop (PLL) circuit 410 that acts as a clock source. The clock signaloutput of the PLL is coupled to an IQ block 411 that generates fourdifferent phases of the PLL clock signal (0°, 90°, 180° and 270°). Allfour phased clock signals are routed to the pixel array and a phaseinterpolator 414. The phase interpolator 414 provides the clock signal415 that is directed to the core drive circuit as a modulation signal.The phase interpolator 414 is part of a delay locked loop (DLL) thatvaries the phase positioning of the clock signal 415 in order toeliminate timing skew (phase mismatch) between the clock signals 416that are directed to the pixel array and the clock signal 415 that isdirected to the core driver.

Here, as discussed above, time-of-flight techniques measure thedifference in time between when light is flashed by the illuminator andwhen its reflection is sensed at the pixel array. Any unaccounted fordifference between these times is reproduced as error or inaccuracy inthe time-of-flight measurement and the profile distance information thatis determined from it. As such, controlling skew between the clocksignal 312, 412 that is presented to the driving transistors within thecore driver and the clocks 416 that are provided to the pixel array havea direct effect on the accuracy of the time-of-flight measurement.

As such, the DLL includes a phase detector 417 that compares the phasedifference between the clock signal that is provided to the drivingtransistors 312, 412 of the core driver circuit slices and the 0° phaseclock signal 416_1 that is directed to the pixel array. In response toany difference in phase between the two, the phase detector 417generates an offset signal that indicates a corrective direction by thephase interpolator 414 that will reduce the offset. In an alternativeimplementation, rather than use the output from buffer 313 as an inputto phase detector 417, an output is taken further downstream from buffer313 such as core driver output 318. Because core driver output 318 mayinclude some additional propagation delay that is imposed in the drivesignal beyond buffer 313, tapping the drive signal at core driver output318 is actually a more accurate signal in terms of the timing edges ofthe emitted optical signal. In an even further implementation, a “dummyslice” may be coupled anywhere downstream from core input 315 to “mimic”the light source drive signal or emitted optical output signal. Forexample, the core driver 301 may include a “duplicate” set of fan-up,inverting buffer, driver slice(s) and “dummy load” circuitry (the laterto represent the load of the VCSEL or LED light sources) to craft asignal that should be nearly identical to the signal received by thelight sources or the actual emitted optical power.

The offset signal from the phase detector 417 is provided to a loopfilter 418. The loop filter 418 integrates the offset signal to generatea control signal to the phase interpolator 414 that adjusts the phase ofthe clock signal 415 that is provided to the core driver circuit thatcorrects for the previously detected offset. Ideally, a steady state isreached in which there is no phase difference between the signal that isprovided to the driver transistors and the 0° phase signal 416_1 that issent to the pixel array. Any other time difference between the actualemission of the light from the light source and the phase of the signalthat is provided to the drive transistors is apt to be fixed and/or anotherwise determinable from, e.g., one or more propagation delays andlight source response times that can be adjusted for as a fixed offset.

The DLL path to the phase interpolator 414 is also intercepted by anoverride multiplexer 419 that allows a user to set, e.g., inconfiguration register space 408, an adjustment to the output of theloop filter 418. For example, if the output of the loop filter 418 is avoltage level that the phase interpolator 414 uses to set the phase ofclock signal 415, circuit 420 may increase or decrease this voltagelevel in increments according to a programmed value from configurationregister space 408. Here, the ability to adjust the loop filter outputvoltage up or down essentially permits the user to impose phase lag orphase lead to clock signal 415 relative to the actual loop filtersetting, which, in turn, corresponds to the deliberate imposition of“offset” into the time-of-flight measurement. In various implementationsthe phase interpolator 414 may receive a digital word as its controlsignal rather than an analog signal. As such, the loop filter 418 may beimplemented as a digital circuit (e.g., a digital accumulator or finitestate machine). Likewise circuit 420 may be implemented as a digitalcircuit (e.g., a digital adder/subtractor) to digitally alter the loopfilter output.

Similar to the optical power override discussed above with respect toFIG. 3c, the deliberate imposition of offset into the phase of clocksignal 415 can be used to simulate the camera system being closer to orfarther from an object of interest. More specifically, both the opticalpower over ride and the DLL over ride can be used together to simulatethe camera being some distance from an object other than its actualdistance. That is, by lessening the optical power and imposingadditional delay to clock signal 415, the Z pixels of the RGBZ sensorwill receive signals of reduced intensity and later in time as if thecamera where farther away from an object than it actually is. Bycontrast, by increasing the optical power and moving the delay of clocksignal 415 earlier in time, the Z pixels of the RGBZ sensor will receivesignals of enhanced intensity earlier in time as if the camera wherecloser to an object than it actually is.

Here, it is pertinent to recognize some alternative embodiments toimposing a simulated distance between the light source and an objectthat is different than an actual distance between the light source andthe object. Embodiments discussed so far include adjusting the amplitudeand phase of the light source drive signal. Conceivably, a strongeroptical signal from a closer object can be simulated by increasing thegain of the depth pixels to capture more charge and therefore generate ahigher amplitude signal from the depth pixels. Likewise, a weakeroptical signal from an object that is farther away can be simulated bydecreasing the gain of the depth pixels to capture less charge andtherefore generate a lower amplitude signal from the depth pixels.

Any combination of these techniques may be used to realize the desiredsimulated distance. As such, various embodiments may include a depthpixel gain adjustment circuit responsive to simulated distanceconfiguration settings to accordingly adjust the gain of the depthpixels.

Additionally a phase interpolator circuit may be used to drive the depthpixel clock signals (e.g., instead of the light source drive signal) toimpose phase adjustments to the depth pixel clock signals to realize thesimulated distance. As such, more generally, the relative phases of thelight source driver signal and the depth pixel clocks may be adjusted tobe closer together in time to simulate an object that is closer, and,the relative phases of the light source driver signal and the depthpixel clocks may be adjusted to be farther apart in time to simulate anobject that is farther away.

The programmable register space 408 for changing the delay of clocksignal 415 may accept any of: 1) a value that specifies a specificchange to be made to the loop filter output; 2) simulated additionaldistance away; 3) simulated additional distance closer. Items 2) and 3)above may be the same configuration space that is used to set theoptical power override. In the case of items 2) and 3) above, circuit420 includes circuitry to determine the correct adjustment to be made tothe loop filter output based on the desired simulated distance. In anembodiment, items 2) and 3) can specify the simulated distances inspecific increments and circuit 420 adjusts the loop filter output inincrements.

In an embodiment, the loop filter 418 is implemented as an analog ormixed signal component that provides the phase interpolator controlsignal as an analog signal (e.g., a voltage). In another embodiment, theloop filter 418 is implemented as a finite state machine that controlsthe interpolator with a digital value. In the former case, circuit 420adjusts the level of the analog signal, in the later case circuit 420adds/subtracts to/from the digital value. Configuration registers 408may also include register space that determines whether the DLL circuitis to operate with or without adjustments from circuit 420. As observedin FIG. 4 , the multiplexer 419 may include an input to receive a phaseinterpolator control input directly from configuration register space408 without any component from the loop filter and circuit 420. Thechannel select input of multiplexer 419 is established in response. In afurther embodiment, parameters of the loop filter 418 itself (e.g., timeconstant, pole frequency, finite state machine combinatorial logiclook-up table values, etc.) can be configured from registers 408.

The timing and control circuitry of FIG. 4 may also generate othertiming and control signals such as timing and control signals for theADC circuits that digitize analog signals from the RGB visible imagecapture pixels of the pixel array as well as RGB visible image capturepixels themselves. For simplicity the circuitry used to generate thesetiming and control signals are not shown in FIG. 4 .

FIG. 5a shows a first methodology that can be performed by embodimentsof the integrated image sensor and light source driver described above.As observed in FIG. 5a, the first methodology includes performing thefollowing within a same semiconductor chip package: generating a drivesignal for a light source; responding to light generated from the drivesignal and reflected from an object to generate analog depth profileinformation for the object; and, digitizing the analog depth profileinformation.

FIG. 5b shows a second methodology that can be performed by embodimentsof the integrated image sensor and light source driver described above.As observed in FIG. 5b the second methodology includes receiving intoconfiguration register space configuration information to simulate adistance between a light source and an object that is different than anactual distance between the light source and the object 511. The methodalso includes generating with a light source driver a light source drivesignal 512. The method also includes sensing with depth capture pixelslight that was generated with the light source drive signal andreflected from an object, wherein, relative phases of the light sourcedrive signal and a clock that is directed to the depth capture pixelsare adjusted to realize the simulated distance and wherein an amplitudeof signals sensed with said depth capture pixels are adjusted to realizethe simulated distance 513.

FIGS. 6a and 6b show alternate embodiments of an integrated image sensorand light source driver. As observed in FIG. 6a, the ADC circuitry 603is on the same upper semiconductor die 610 as the pixel array 601instead of being on the lower semiconductor die 602 having the lightsource driver circuit 605. As observed in FIG. 6b, the uppersemiconductor die 610 is a complete image sensor having the pixel array601, ADC circuitry 603 and timing and control circuitry 604. The lowersemiconductor die 610 has the light source driver circuitry 605. Stillother embodiments may have different portions of any of the ADCcircuitry, timing and control circuitry and light source driver on boththe upper and the lower semiconductor die.

FIG. 7 shows an integrated traditional camera and time-of-flight imagingsystem 700. The system 700 has a connector 701 for making electricalcontact, e.g., with a larger system/mother board, such as thesystem/mother board of a laptop computer, tablet computer or smartphone.Depending on layout and implementation, the connector 701 may connect toa flex cable that, e.g., makes actual connection to the system/motherboard, or, the connector 701 may make contact to the system/mother boarddirectly.

The connector 701 is affixed to a planar board 702 that may beimplemented as a multi-layered structure of alternating conductive andinsulating layers where the conductive layers are patterned to formelectronic traces that support the internal electrical connections ofthe system 700. Through the connector 701 commands are received from thelarger host system such as configuration commands that write/readconfiguration information to/from configuration registers within thecamera system 700.

An RGBZ image sensor and light source driver 703 are integrated into asame semiconductor die package that is mounted to the planar board 702beneath a receiving lens 702. The RGBZ image sensor includes a pixelarray having different kinds of pixels, some of which are sensitive tovisible light (specifically, a subset of R pixels that are sensitive tovisible red light, a subset of G pixels that are sensitive to visiblegreen light and a subset of B pixels that are sensitive to blue light)and others of which are sensitive to IR light. The RGB pixels are usedto support traditional “2D” visible image capture (traditional picturetaking) functions. The IR sensitive pixels are used to support 3D depthprofile imaging using time-of-flight techniques. Although a basicembodiment includes RGB pixels for the visible image capture, otherembodiments may use different colored pixel schemes (e.g., Cyan, Magentaand Yellow). The integrated image sensor and light source driver 703 mayalso include ADC circuitry for digitizing the signals from the imagesensor and timing and control circuitry for generating clocking andcontrol signals for the pixel array, the ADC circuitry and the lightsource driver circuit.

The planar board 702 may likewise include signal traces to carry digitalinformation provided by the ADC circuitry to the connector 701 forprocessing by a higher end component of the host computing system, suchas an image signal processing pipeline (e.g., that is integrated on anapplications processor).

A camera lens module 704 is integrated above the integrated RGBZ imagesensor and light source driver 703. The camera lens module 704 containsa system of one or more lenses to focus received light through anaperture of the integrated image sensor and light source driver 703. Asthe camera lens module's reception of visible light may interfere withthe reception of IR light by the image sensor's time-of-flight pixels,and, contra-wise, as the camera module's reception of IR light mayinterfere with the reception of visible light by the image sensor's RGBpixels, either or both of the image sensor's pixel array and lens module703 may contain a system of filters arranged to substantially block IRlight that is to be received by RGB pixels, and, substantially blockvisible light that is to be received by time-of-flight pixels.

An illuminator 705 composed of a light source array 707 beneath anaperture 706 is also mounted on the planar board 701. The light sourcearray 707 may be implemented on a semiconductor chip that is mounted tothe planar board 701. The light source driver that is integrated in thesame package 703 with the RGBZ image sensor is coupled to the lightsource array to cause it to emit light with a particular intensity andmodulated waveform.

In an embodiment, the integrated system 700 of FIG. 7 support threemodes of operation: 1) 2D mode; 3) 3D mode; and, 3) 2D/3D mode. In thecase of 2D mode, the system behaves as a traditional camera. As such,illuminator 705 is disabled and the image sensor is used to receivevisible images through its RGB pixels. In the case of 3D mode, thesystem is capturing time-of-flight depth information of an object in thefield of view of the illuminator 705. As such, the illuminator 705 isenabled and emitting IR light (e.g., in an on-off-on-off . . . sequence)onto the object. The IR light is reflected from the object, receivedthrough the camera lens module 704 and sensed by the image sensor'stime-of-flight pixels. In the case of 2D/3D mode, both the 2D and 3Dmodes described above are concurrently active.

FIG. 8 shows a depiction of an exemplary computing system 800 such as apersonal computing system (e.g., desktop or laptop) or a mobile orhandheld computing system such as a tablet device or smartphone. Asobserved in FIG. 8 , the basic computing system may include a centralprocessing unit 801 (which may include, e.g., a plurality of generalpurpose processing cores) and a main memory controller 817 disposed onan applications processor or multi-core processor 850, system memory802, a display 803 (e.g., touchscreen, flat-panel), a local wiredpoint-to-point link (e.g., USB) interface 804, various network I/Ofunctions 805 (such as an Ethernet interface and/or cellular modemsubsystem), a wireless local area network (e.g., WiFi) interface 806, awireless point-to-point link (e.g., Bluetooth) interface 807 and aGlobal Positioning System interface 808, various sensors 809_1 through809_N, one or more cameras 810, a battery 811, a power managementcontrol unit 812, a speaker and microphone 813 and an audiocoder/decoder 814.

An applications processor or multi-core processor 850 may include one ormore general purpose processing cores 815 within its CPU 401, one ormore graphical processing units 816, a main memory controller 817, anI/O control function 818 and one or more image signal processorpipelines 819. The general purpose processing cores 815 typicallyexecute the operating system and application software of the computingsystem. The graphics processing units 816 typically execute graphicsintensive functions to, e.g., generate graphics information that ispresented on the display 803. The memory control function 817 interfaceswith the system memory 802. The image signal processing pipelines 819receive image information from the camera and process the raw imageinformation for downstream uses. The power management control unit 812generally controls the power consumption of the system 800.

Each of the touchscreen display 803, the communication interfaces804-807, the GPS interface 808, the sensors 809, the camera 810, and thespeaker/microphone codec 813, 814 all can be viewed as various forms ofI/O (input and/or output) relative to the overall computing systemincluding, where appropriate, an integrated peripheral device as well(e.g., the one or more cameras 810). Depending on implementation,various ones of these I/O components may be integrated on theapplications processor/multi-core processor 850 or may be located offthe die or outside the package of the applications processor/multi-coreprocessor 850.

In an embodiment one or more cameras 810 includes an integratedtraditional visible image capture and time-of-flight depth measurementsystem having an RGBZ image sensor and light source driver integrated ina same semiconductor chip package. Application software, operatingsystem software, device driver software and/or firmware executing on ageneral purpose CPU core (or other functional block having aninstruction execution pipeline to execute program code) of anapplications processor or other processor may direct commands to andreceive image data from the camera system.

In the case of commands, the commands may include entrance into or exitfrom any of the 2D, 3D or 2D/3D system states discussed above.Additionally, commands may be directed to configuration space of theintegrated image sensor and light source driver to implement any of theconfigured settings discussed above with respect to FIGS. 1a,b through6a,b, including but not limited to a configuration that causes theintegrated image sensor and light source driver to simulate the camerabeing closer to or farther from an object in its field of view that thecamera actually is.

Embodiments of the invention may include various processes as set forthabove. The processes may be embodied in machine-executable instructions.The instructions can be used to cause a general-purpose orspecial-purpose processor to perform certain processes. Alternatively,these processes may be performed by specific hardware components thatcontain hardwired logic for performing the processes, or by anycombination of programmed computer components and custom hardwarecomponents.

Elements of the present invention may also be provided as amachine-readable medium for storing the machine-executable instructions.The machine-readable medium may include, but is not limited to, floppydiskettes, optical disks, CD-ROMs, and magneto-optical disks, FLASHmemory, ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards,propagation media or other type of media/machine-readable mediumsuitable for storing electronic instructions. For example, the presentinvention may be downloaded as a computer program which may betransferred from a remote computer (e.g., a server) to a requestingcomputer (e.g., a client) by way of data signals embodied in a carrierwave or other propagation medium via a communication link (e.g., a modemor network connection).

In the foregoing specification, the invention has been described withreference to specific exemplary embodiments thereof. It will, however,be evident that various modifications and changes may be made theretowithout departing from the broader spirit and scope of the invention asset forth in the appended claims. The specification and drawings are,accordingly, to be regarded in an illustrative rather than a restrictivesense.

The invention claimed is:
 1. An apparatus, comprising: a semiconductorchip package comprising an image sensor, a light source driver circuitand a timing circuit integrated in a same semiconductor chip package,said image sensor comprising visible light pixels and depth pixels, saiddepth pixels to sense light generated with a light source drive signal,said light source driver circuit comprising an output to provide saidlight source drive signal, said image sensor comprising an input toreceive a first clock signal for said depth pixels, said timing circuitcomprising a first output to provide said first clock signal, said lightsource driver circuit comprising an input to receive a second clocksignal for said light source drive signal, and said timing circuitcomprising an output to provide said second clock signal.
 2. Theapparatus of claim 1 wherein said semiconductor chip package furthercomprises configuration registers to program said timing circuit is tobe programmed from configuration registers that reside within saidsemiconductor chip package.
 3. The apparatus of claim 1 wherein saidsemiconductor chip package comprises a first semiconductor chip and asecond semiconductor chip, and wherein said image sensor is disposed ona said first semiconductor chip and at least one of said light sourcedriver circuit and said timing circuit are disposed on a said secondsemiconductor chip.
 4. The apparatus of claim 3 wherein said firstsemiconductor chip is stacked on said second semiconductor chip.
 5. Theapparatus of claim 4 wherein said second semiconductor chip furthercomprises conductive vias within its substrate coupled to conductiveballs and/or bumps on a bottom surface of said semiconductor chippackage.
 6. The apparatus of claim 1 wherein said apparatus furthercomprises analog-to-digital conversion circuitry integrated within saidsemiconductor chip package, said analog-to-digital conversion circuitryto digitize analog signals generated by said depth pixels.
 7. Theapparatus of claim 1 wherein said timing circuit is to generatequadrature clock signals for said image sensor.
 8. A method, comprising:generating a first clock signal and a second clock signal with a timingcircuit that is within a semiconductor chip package; generating a lightsource drive signal from the first clock signal with a light sourcedriver circuit that is integrated within the semiconductor chip package;and sensing visible light with visible light pixels of an image sensorthat is integrated within the semiconductor chip package; and,generating depth information with depth pixels of the an image sensorthat is integrated within the semiconductor chip package, the generatingof the depth information comprising the image sensor receiving thesecond clock signal and receiving light generated with the light sourcedrive signal.
 9. The method of claim 8 further comprising programmingconfiguration registers for said timing circuit that reside within saidsemiconductor chip package.
 10. The method of claim 8 wherein said imagesensor is disposed on a first semiconductor chip and at least one ofsaid light source driver circuit and said timing circuit is disposed ona second semiconductor chip and the method further comprisestransmitting said first clock signal and said second clock signal fromthe second semiconductor chip to the first semiconductor chip.
 11. Themethod of claim 10 wherein said first semiconductor chip is stacked onsaid second semiconductor chip.
 12. The method of claim 11 wherein saidsecond semiconductor chip further comprises conductive vias within itssubstrate coupled to conductive balls and/or bumps on a bottom surfaceof said semiconductor chip package.
 13. The method of claim 8 furthercomprising performing analog-to-digital conversion within saidsemiconductor chip package to digitize analog signals generated by saiddepth pixels.
 14. A computing system, comprising: a plurality of generalpurposeone or more processors; a system memory; a memory controllercoupled between the system memory and the general purpose one or moreprocessors; and a semiconductor chip package comprising an image sensor,a light source driver circuit and a timing circuit integrated in a samesemiconductor chip package, said image sensor comprising visible lightpixels and depth pixels, said depth pixels to sense light generated witha light source drive signal, said light source driver circuit comprisingan output to provide said light source drive signal, said image sensorcomprising an input to receive a first clock signal for said depthpixels, said timing circuit comprising a first output to provide saidfirst clock signal, said light source driver circuit comprising an inputto receive a second clock signal for said light source drive signal, andsaid timing circuit comprising an output to provide said second clocksignal.
 15. The computing system of claim 14 wherein said semiconductorchip package further comprises configuration registers to program saidtiming circuit is to be programmed from configuration registers thatreside within said semiconductor chip package.
 16. The computing systemof claim 14 wherein said semiconductor chip package further comprises afirst semiconductor chip and a second semiconductor chip, and whereinsaid image sensor is disposed on a the first semiconductor chip and atleast one of said light source driver circuit and said timing circuitare disposed on a the second semiconductor chip.
 17. The computingsystem of claim 16 wherein said first semiconductor chip is stacked onsaid second semiconductor chip.
 18. The computing system of claim 17wherein said second semiconductor chip further comprises conductive viaswithin its substrate coupled to conductive balls and/or bumps on abottom surface of said semiconductor chip package.
 19. The computingsystem of claim 14 wherein said apparatus further comprises furthercomprising analog-to-digital conversion circuitry integrated within saidsemiconductor chip package, said analog-to-digital conversion circuitryto digitize analog signals generated by said depth pixels.
 20. Thecomputing system of claim 14 wherein said timing circuit is to generatequadrature clock signals for said image sensor.
 21. The computing systemof claim 14, wherein said image sensor further comprises visible lightpixels.
 22. The apparatus of claim 1, wherein said image sensor furthercomprises visible light pixels.
 23. The method of claim 8, furthercomprising: sensing visible light with visible light pixels of the imagesensor.